The L2 Cache
The purpose of cache memory is to enable the processor to run in a
constant state of flux. Whenever the processor is made to wait on data or instructions it
is that much slower. Memory caching is effective because most programs access the same
data or instructions over and over. By keeping as much of this information as possible in
cache, the computer avoids accessing the slower system memory.
Cache memory is made up of much faster SRAM or static random access memory. Since the memory stored in SRAM is static it does not need to undergo the constant refreshment required by DRAM. This constant refreshment is time consuming making DRAM unsuitable for the immediate needs of the processor.
While DRAM SIMMs supports access times of about 60 nanoseconds, SRAM can give access times as low as 05 nanoseconds. In addition, its cycle time is much shorter than that of DRAM because it does not need to pause between accesses. Unfortunately, it is also much more expensive to produce than DRAM. Due to its high cost, SRAM is often used only as a memory cache
SRAM memory cache that is built into the architecture of the processor is called Level 1 (L1) cache. The Intel 80486 processor, for example, contains an 8K-memory cache, and the Pentium has a 16K cache. Some of the newer chips like those from AMD and Cyrix contain as much as 64k onboard. Most modern PCs also come with external cache memory, called Level 2 (L2) caches. These caches sit between the CPU and the system memory or DRAM. Like L1 caches, L2 caches are composed of SRAM but they are much larger.
There are multiple types of SRAM that can be used as cache memory. In order to keep this in simple terms the easiest way to compare them is to compare the number of SRAM access's per cycle during a burst. Today's processors support either interleaved or linear burst schemes. When using the burst mode for cache access, the first access takes the processor two cycles. The second, third and fourth accesses require only one cycle. A zero-wait-state cache would add no delays to this 2-1-1-1 sequence but as bus frequencies increase, maintaining this zero-wait-state cache becomes increasingly difficult and extremely expensive for most system design.
Pretty much fallen by the wayside Asynch SRAM was used for years since the 80386 when the first L2 cache came out. The main reason this type of cache RAM was used was that it was faster to access than DRAM and depending on your CPU clock you still can get it in 20, 15 or 12 ns access times. The shorter the access/data times, the quicker it is and the shorter the burst accesses to it can be selected. However, as the name implies, it's not fast enough to be able to be accessed synchronously. This means that the processor has to wait on this cache RAM but slightly less than it has to wait for DRAM.
Synchronous Burst SRAM
Running at bus speeds up to 66 MHz the Sync Burst SRAM is the fastest available. This is because if the CPU doesn't run too fast, the Sync Burst SRAM can offer the data synchronously, which means that there's no delay to the processors 2-1-1-1 burst read. The Sync Burst SRAM delivers the data in 2-1-1-1 burst cycles.
However, when the Processor bus speed exceeds this 66 MHz plateau (as all "Super" 7 systems do) the Sync Burst SRAM maxes out and delivers in 3-2-2-2 bursts, which is significantly slower than Pipelined Burst SRAM.
Pipelined Burst SRAM
Currently the standard found on almost every new mainboard. Pipelining is created by employing input or output registers. Loading these registers takes an extra lead-off cycle, but once loaded allows early access to the next address location while supplying the data from the current location.
Pipelined Burst SRAM is the cheapest and fastest cache RAM for new systems with 75 MHz bus speeds or above. Theoretically it should work without error at bus speeds up to 133 MHz, it delivers in 3-1-1-1 bursts across the FSB spectrum.
It's access/data times generally run at 4.5 to 8 ns.
It wasn't too long ago that the 512kb L2 cache was the hot upgrade on the newest
motherboards, replacing the old' standby 256kb. Our new generation of SS7 chipsets however
support up to 2MB of L2 cache and many systems engineers are still scratching their heads
pondering whether or not this is either useful or sensible.
Prior to the release of Windows 95 there was no real need to install more than a 256kB L2 Cache unless you had to have more than 64MB RAM. Windows 95 benchmarks consistently proved that a cache size of 512 kb was increasing system performance even with as little as 16MB of installed RAM.
In 32 bit multi-thread, multi-tasking operating systems such as Windows 95 & 98, NT 4.0 and the long awaited NT 5.0, an increased L2 cache size, up to 2 MB, does indeed make sense and will result in increased performance simply due to the larger size of the actual programs and the larger number of programs which are running simultaneously. Many of the SS7 mainboards currently available come with a 1MB L2 cache as standard and although modest the latest benchmarks do show some performance increase over their 512kb L2 brothers. Because of this we here at MediaTek foresee an even greater performance increase in the future when developers and programmers make more efficient use of the larger cache size and consequently recommend going for the larger L2 cache if at all possible.
1998/99 2000 MediaTek
last updated Sept. 30.1998