SiS530 Part II
SiS530's Host Interface
The SiS 530's Host Interface has been designed to support both the wide range of existing socket 7 CPUs as well as the integrated 3D VGA Controller. The 530 supports the CPUs L1 write-back or write-through caching policies as well as the L2 write-back mode. Support for existing CPUs pipelined addressing modes comes in the form of its ability to assert a next address signal except during a single read DRAM cycle. The Host Interface also is capable of issuing an address hold to the CPU in response to the assertion of a PCI master request but doesn't issue a PCI Bus Grant until both the CPU/PCI Posted Write Buffer and memory write buffer are emptied. Destinations of CPU initiated cycles are also decoded by the Host Interface, with memory cycles forwarded to the DRAM controller while AGP and PCI I/O cycles are forwarded to their respective buses.
The L2 Cache Controller used a direct-mapped scheme that can be configured in either write-back or write-through modes. It supports cache sizes from 256k - 2M according to 8bit TAG address lines.
Supported L2 Cache Sizes
|Cache Size||Tag RAM||Cacheable Size|
SiS 530's DRAM Controller supports up to 1.5GB of single or double sided 64-bit Synchronous DRAM in industry standard DIMMs with 6 CS# lines permitting up to three double sided DIMM slots and DRAM types can be mixed on a bank by bank configuration. There is a built-in CPU to memory posted write buffer 8 QWord deep keeping all write accesses to DRAM from the CPU buffered, and an arbiter to pass or translate information from outside to the DRAM Controller and also to determine which master gets highest priority to the DRAM. Full refresh functionality is asserted with up to 12 refresh queues on two levels of refresh priority with SiS 530 generating a new refresh request every 15.6µs.
The PCI bridge of the SiS 530 consists of a PCI arbiter, PCI master bridge and PCI target bridge. The PCI arbiter determines which master requires control of the PCI bus, while the PCI master bridge forwards transactions from the Host bus. The PCI target bridge claims PCI cycles for DRAM as required by PCI master devices. SiS 530 can operate the PCI asynchronously with the CPU clock and target and master bridges can be set at separate speeds.
SiS 530 supports a full function PCI IDE Controller capable of PIO, DMA and Ultra DMA modes.
With two 64-byte FIFO associated with each of the two IDE channels data can be immediately introduced into the FIFO by units in word or double-word. All accesses to the IDE port go through FIFO whether or not prefetch/postwrite is enabled, but access to command or control ports bypass FIFO. This allows the host to access command or control when FIFO is not empty. The large 64-byte FIFO is backwards compatible but is mainly intended to support Ultra DMA because a small FIFO can create bottlenecks slowing system performance.
But Just how well does it work???
I found the SiS 530/5595 demo board to be extremely efficient and remarkably fast. Although I was never able to reach any level of what I would deem stability at front side bus speeds exceeding the 100MHz level. Using the 100MHz front side busl, however, the SiS 530/5595 surpassed many if not most of the super7 platform mainboards currently available.
Testbed Configuration for SiS 530/5595
|L2 Cache||1024k Pipelined Burst SRAM|
|Memory|| 64MB PC100 (CAS
Corsair CM 654S64-BX2
|Hard Disk Drive||Quantum Fireball EX 12.4G|
|Operating System||Windows 98|
Since I am not an engineer, I had quite a bit of difficulty configuring the amazing ROM BIOS that was listed simply as Evaluation ROM - Not For Sale, because the settings were quite technical. But after some careful study and a little trial and error, it became quite easy to determine the correct settings for the different CPUs used in testing. Especially after receiving the third BIOS update that was furnished by the fine technical and marketing staff at SiS. And I would like to express my deepest thanks to Sylvia, Jessie, and Jacky of Silicon Integrated Systems, all of whom were most helpful in providing all of the necessities I required for learning to use the demoboard.
I began with a clean HDD and after loading the operating system, extra drivers and benchmark programs I ran Business Winstone 98 and was amazed at the high score that it rendered. I ran Business Winstone 98 five times for each of the processors below at their default clock and FSB settings and averaged the scores to produce the chart below...
As you can see, from the chart above, the SiS 530/5595 is quite a speedy performer and remarkably stable at the 66MHz, 75MHz, 83MHz and 100MHz. front side bus speeds. It would not however complete a full run of the Business Winstone 98 benchmark at 112MHz or 124MHz external CPU speeds (stopping primarily during JAVA cycles in the Browsers benchmark) and would not boot at 133MHz even though the setting was available.
The scores above put mainboards equipped with SiS 530 in a very good light as to the sub $800.00 system is concerned, and in our next installment we'll take a look at the SiS 530's built in 2D/3D AGP VGA controller and also give our total overall impression and recommendations.