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The Chipset is one of the most important factors to consider before deciding which board to buy. Basically, the chipset is a very sophisticated communications router that allows the peripherals to communicate with the processor and vice-versa. It is also the medium that allows both the processor, and now the advanced graphics port, access to the main memory or RAM. The chipset, along with the Level 2 Cache is also instrumental in determining the cacheable memory area so necessary to graphical user interface operating systems such as Windows 95 and 98. Since there are really only two chipsets currently available for true Super 7 systems, Lets move on and cover them individually…

100MHz Chipset  Comparison Table


Apollo MVP3
Aladdin V
SiS 530
Chipset Packaging
North Bridge VT82C598
BGA 476pin
BGA 456pin
South Bridge VT82C586B
PQFP 208pin
BGA 328pin
Bus Speeds 66/75/83/95/100 66/75/83/100 66/75/83/95/100
IDE UDMA/33 UDMA/33 UDMA/33/66
Processor Support
Pentium® Y Y Y
Cyrix 6x86TM Y Y Y
6x86 Linear Burst Y Y Y
K6 Write Allocation Y Y Y
L2 Cache
L2 Cache type PB PB PB
Max L2 Cache 2MB 1MB 2MB
Max Cachable Area 256MB 128MB 256MB
DRAM Interface
Max Main Memory 1GB 1GB 1.5GB
EDO 5-2-2-2 5-2-2-2 5-2-2-2
SDRAM 6-1-1-1 6-1-1-1 6/7-1-1-1

ALI Aladdin V AGP Chipset - 66/100 MHz Front Side Bus
Aladdin V M1541 M1543C

Aladdin-V is the fifth generation 586 chipset from AcerLabs. Aladdin-V consists of
two BGA chips to give state of the art features to the 586-class system. Creating a stable architecture for the most engaging multimedia, multi-taking operating systems and software applications.

M1541 includes the higher CPU bus frequency - up to 100 MHz - interface for
all socket 7 compatible processors. It also provides a PBSRAM and Memory Cache L2 controller, internal MESI tag bits (16Kx2) and Tag RAM (16Kx10) to enhance performance. It's high performance FPM/EDO/SDRAM DRAM
controller, PCI 2.1 compliant bus interface,  and smart deep buffer design for CPU
-to-DRAM, CPU-to-PCI, and PCI-to-DRAM achieve superior system performance. M1541 also provides the most flexible 64-bit memory bus interface making it supremely DRAM upgradeable with ECC/Parity support to enhance system reliability.

With it's current AGP interface design, the dedicated PCI-66 AGP interface runs simultaneously with the CPU and PCI interface. The deep buffer of the read and write
buffer design makes more efficient utilization of memory bandwidth . The
interface not only supports the AGP 66MHz PCI standard, but also the AGP 1X
and 2X sideband address function.

With the concurrent bus design, PCI-to-PCI access can run concurrently
with CPU-to-L2 and CPU-to-DRAM access, PCI-to-DRAM access can run
concurrently with CPU-to-L2 access.  M1541 also supports the "snoop ahead"
feature making it capable of achieving the PCI master full bandwidth access speed - (133Mbytes). M1541 also provides the enhanced power management features including ACPI support, suspend DRAM refresh, and internal chip power control to support
Microsoft On Now technology operating systems.

M1543 provides the best desktop system solution. M1543 integrates ACPI
support, green function, 2-channel dedicated Ultra-33 IDE Master controller
, 2-port USB controller, SMBus controller, PS/2 Keyboard/Mouse controller
and the Super I/O (Floppy Disk Controller, 2 serial port/1 parallel port) support.

VIA Apollo mVP3 AGP Chipset 66/100 MHz Front Side Bus

The Apollo MVP3 is a high performance, cost effective, and energy efficient chip set for the implementation of AGP, PCI, and ISA in desktop and notebook PC's with a front side bus of 66MHz to 100 MHz based on 64-bit Socket-7 super-scalar processors.

The Apollo MVP3 chipset consists of the VT82C598AT system controller, and the VT82C586B PCI to ISA bridge. The VT82C598AT system controller provides outstanding performance between the CPU, optional synchronous cache, DRAM, AGP bus, and the PCI bus with pipelined burst, and simultaneous operation. The DRAM controller supports standard FPM, EDO, SDRAM, and DDR SDRAM. The VT82C598AT meets the AGP Specification 1.0 and features documented support for 66/75/83/100 MHz CPU bus frequencies and the 66MHz AGP bus frequency.

The MVP3 is PC97 compatible using VT82C586B South Bridge with ACPI Power Management.
Includes UltraDMA-33 EIDE, USB, and Keyboard/PS2-Mouse Interfaces with RTC/CMOS on chip. Provides single chip implementation for 64-bit Socket-7 CPU, 64-bit system memory, 32-bit PCI and 32-bit AGP interfaces. Maintains 3.3V and sub-3.3V interface to CPU and also 3.3V (5V tolerant) DRAM, AGP,and PCI interface. Full support for 33 MHz operation on the primary PCI bus and 66 MHz PCI operation on the AGP bus.
It also provides concurrent CPU and AGP access and Fast Page, EDO, SDRAM, and DDR SDRAM support.

SiS530 - Host, PCI, 3D A.G.P. Video/Graphics & Memory Controller

The P5 A.G.P./VGA chipset, SiS530/5595, provides a high performance/cost index Desktop/Mobile solution for the Intel Pentium P54C/P55C, AMD K5/K6/K6-II, and Cyrix M1/M2 3D A.G.P. with VGA system.

The Host, PCI, 3D A.G.P. Video/Graphics & Memory Controller, SiS530 integrates the Host-to-PCI bridge, the PCI interface, the L2 cache controller, the DRAM controller, the high performance hardware 2D/3D VGA controller, and the PCI IDE controller.
The Host interface supports Synchronous /Asynchronous Host/DRAM clocking configuration to eminently improve the system performance and DRAM compatibility issues.
The L2 cache controller can support up to 2 M P.B. SRAM, and the DRAM controller can support SDRAM memory up to 1.5 GBytes with three double-sided SDRAM DIMMs configuration. The cacheable DRAM sizes support up to 256 Mbytes.

The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the Ultra DMA33/66 function that support the data transfer rate up to 66 MB/s. It provides the separate data path for two IDE channels that can eminently improve the performance under the multi-tasking environment.

The A.G.P. internal interface is supported for integrated H/W 3D VGA controller. The integrated VGA controller is a high performance and targeted at 3D graphics application. In addition, the integrated 3D Video/Graphics controller adopts the 64bits 100MHz host bus interface high technology to improve the performance eminently. To cost-effective the PC system, the share system memory architecture will be adopted and it can flexibly using the 2MB, 4MB and 8MB frame buffer size from programming the system BIOS. To enhance the system performance, SiS530 also supports the local frame buffer solution.
In addition to providing the standard interface for CRT monitors, it also provides the Digital Flat Panel Port (DFP) for a standard interface between a personal computer and a digital flat panel monitor. This port allows a host computer to connect directly to an external flat panel monitor without the need for analog-to-digital conversion found in most flat panel monitors today.

The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the DDMA, PC/PCI DMA and Serial IRQ capability, the ACPI/Legacy PMU, the Data Acquisition Interface, the Universal Serial Bus host/hub interface, and the ISA bus interface which contains the ISA bus controller, the DMA controllers, the interrupt controllers, the Timers and the Real Time Clock (RTC). It also integrates the Keyboard Controller and PS/2 mouse interface that can support keyboard power on function for users to power on system by entering the hot key or password from keyboard.

The built-in USB controller, which is fully compliant to OHCI (Open Host Controller Interface), provides two USB ports capable of running full/low speed USB devices.
The Data Acquisition Interface offers the ability of monitoring and reporting the environmental condition of the PC. It could monitor 5 positive analog voltage inputs, 2 Fan speed inputs, and one temperature input.
In addition, SiS5595 also supports ACPI function to meet Advanced Configuration and Power Interface (ACPI) 1.0 specification for Windows 98 environment, it can support power-management timer, Power button, Real-time clock alarm wake up, more sleeping state, ACPI LED for sleeping and working state, LAN wake up, Modem Ring In wake up, and OnNow initiative function.

For complete specifications click the link below...

Although the Aladdin V has a slight performance edge with it's on-chip L2 cache (16k x 2) and built in 16k  x 10-bit Tag RAM, theMVP3 more than makes up for it with the ability to run the SDRAM clock at the same speed as the AGP clock thus eliminating the need for PC100 SDRAM to maintain a front side bus speed of 100 MHz.   We will have to wait a bit to see the features of the SiS chipset in their full light but their specification looks most promising...

BIOS FAQ ] BIOS Updates ] AMD-750 Chipset ] SiS 530/5595 ] SiS540 Preview Pt. I ] Intel i810 Chipset ] Intel's i810E Chipset ]


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